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Therefore, each processor is configured to have the same configuration of its local memory as the other processors. The multi-processor ARM simulation framework does not support a configurable multilevel memory hierarchy. The memory hierarchy consists of instruction and data caches, scratchpads and the shared main memory. Currently, an effort is being made to integrate MEMSIM into the multi-processor simulator. 1 Energy Model The multi-processor ARM simulation framework includes energy models for the processors, the local memories and the interconnect.
The presented approaches are not entirely novel as similar techniques are already known. They are presented in this chapter for the sake of completeness, as the advanced scratchpad allocation approaches presented in the subsequent chapters improve and extended these approaches. The rest of the chapter is organized as follows: The following section provides an introduction to the non-overlayed scratchpad allocation approaches, which is followed by the presentation of a motivating example. 3 surveys the wealth of work related to non-overlayed scratchpad allocation approaches.
Each instruction is 2 bytes or 16 bits wide. Therefore, the energy consumed by the memory hierarchy when the scratchpad memory is not utilized is 2, 939, 787∗10+203, 694∗20 = 33, 471, 750 units. The product of the number of instruction fetches (2, 939, 787) (cf. 1) and the energy per access (10) to the main memory computes the energy consumed due the instruction fetches. Similarly, the energy consumed due to the data accesses can be computed. The sum of the energy consumed due to instruction fetches and data accesses is the energy consumed by the memory hierarchy.